User guide

22-24
SystemVerilog Design Constructs
begin
assign l2=1;
l3=1;
#10 force l1=0;
force l2=0;
force l3=0;
#10 release l1;
release l2;
release l3;
end
endmodule
Signal l1 is continuously assigned a value of 1 at simulation time 10.
Assuming a rising edge on the clock signal at simulation time 100, a
procedural continuous assignment assigns the value of 1 to signal l2
and a procedural assignment assigns the value of 1 to signal l3.
At simulation time110, all three signals are forced to a 0 value.
At simulation time 120, when VCS executes all three release
statements, signals l1 and l2 return to their 1 values, but signal l3
remains at 0 until the next rising edge on the clock.
Integer Data Types
The SystemVerilog LRM lists the following data types as integer data
types:
shortint int longint byte bit logic reg integer time
All of these data types can hold an integer value. With the exception
of the time data type, you can force a value on to an entire signal
with these data types or a bit-select or part-select of these data types.