User guide

22-23
SystemVerilog Design Constructs
Error-[IFRLHS] Illegal force/release left hand side
Force/Release of an unpacked array which is driven by
a mixture of structural and procedural assignments is not
valid
The offending expression is signal_name
"mult_driver.v", 10: force signal_name[1] = 1;
This restriction does not hold for unpacked structures, see
"Structures" on page 22-27.
Release Behavior
When VCS executes a release statement on a SystemVerilog
variable, the release behavior depends on how that variable obtained
the value it had before VCS executed the previous force statement
on it.
• If it was a structural driver, which is to say a connection to a module
or primitive instance or by a continuous assignment or a
procedural continuous assignment, the variable returns to its
previous value immediately.
• If it was a behavioral driver, otherwise known as a procedural
assignment statement, the variable returns to that previous value
when or if VCS executes the procedural assignment statement
again. Until VCS executes the assignment again, the variable
keeps its forced value.
The following SystemVerilog module illustrates this behavior:
module test;
logic l1, l2, l3;
.
.
.
assign #10 l1=1;
.
.
.
always @(posedge clk)