User guide

22-21
SystemVerilog Design Constructs
endmodule
Automatic Variables
You cannot force a value on to an automatic variable. For example:
task automatic my_aut_task;
.
.
.
begin
.
.
.
#1 force mat=1; // causes this warning:
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.
.
end
endtask
Doing so makes the task static and VCS displays the following
warning message:
Warning-[MNA] Making Task or Function Non-Automatic
Disable/Force/Release/Assign/Deassign inside Automatic Task
is not supported.
"filename.v", line_number:
task automatic task_name;
Also any cross-reference to or from an automatic variable makes the
task static. This happens with a force statement, but also with any
kind of assignment statement. All of the assignment statements and
force statements in the following code result in VCS compiling the
task as a static task:
initial
begin
#5 r5=my_aut_task.mat;
#5 my_aut_task.mat =1;
#5 force my_aut_task.mat=1;
#5 force r5=my_aut_task.mat;
end