User guide

22-20
SystemVerilog Design Constructs
As you can see, in SystemVerilog, you can write to a variable using
a continuous assignment, connecting it to an output terminal of a
primitive, or an output port of a module instance. Doing so is called
using a structural driver.
There are some limitations on structural drivers on variables:
• A variable cannot have a behavioral driver (assigned a value by
a procedural assignment statement) and a structural driver.
• A variable, unlike a net, cannot have multiple structural drivers.
• A variable still cannot connect to an inout port of a module
definition.
Note:
You can also declare a variable to be an input port, this is also
using a structural driver, See "New Port Connection Rules for
Variables" on page 22-59.
Force and Release on SystemVerilog Variables
You can enter force and release statements for SystemVerilog
data types. The following SystemVerilog code declares such data
types and force and release statements for them:
module test;
int int1,int2;
initial
begin
force int1=100;
force int2=100;
#100 release int1;
release int2;
end