User guide

22-19
SystemVerilog Design Constructs
The testbench constructs that you can enter outside programs with
this option are as follows:
classes associative arrays dynamic arrays
SystemVerilog named events
For descriptions and examples of these constructs see Chapter 24,
"SystemVerilog Testbench Constructs".
Writing To Variables
SystemVerilog changes one of the basic concepts of Verilog: that
variables are only written to by procedural statements. In
SystemVerilog there are several other ways to write to a variable, as
the following code example illustrates:
module dat;
logic log1,log2,log3;
longint loi1;
byte byt1;
wire w1;
assign log1=w1; //continuous assignment to logic
assign loi1=w1; //continuous assignment to longint
assign byt1=w1; //continuous assignment to byte
buf b1 (log2,w1); //connect to output terminal
dev dev1(log3,w1); //connect to output port
endmodule
module dev(output out,input in);
assign out=in;
endmodule