User guide

22-18
SystemVerilog Design Constructs
Figure 22-2 A SystemVerilog Part Select
The second of the two previous assignment statements:
log3[6][11:10]=2’b00;
This is an assignment to a slice. A slice is a joint part select in
contiguous elements of a multidimensional array. This slice
assignment is shown in Figure 22-3.
Figure 22-3 A SystemVerilog Slice
SystemVerilog Testbench Constructs Outside
Programs
SystemVerilog testbench constructs outside programs, for example
in modules, packages and in $root, is an LCA feature requiring a
special license. SystemVerilog packages are described in
"SystemVerilog Packages" on page 22-46.
You enable testbench constructs outside programs with the
-ntb_opts dtm compile-time option and keyword argument. The
keyword name comes from “dynamic types in modules.”
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