User guide

22-17
SystemVerilog Design Constructs
Figure 22-1 Packed and Unpacked Multi-dimensional Array
The first of the previous two assignment statements:
log3[6][11][1:0]=2’b11;
This is an assignment to a part select. It is an assignment to
contiguous bits on a single packed dimension.
11 10 9 8 7 6 5 4 3 2 1 0
1
0
11 10 9 8 7 6 5 4 3 2 1 0
1
0
11 10 9 8 7 6 5 4 3 2 1 0
1
0
11 10 9 8 7 6 5 4 3 2 1 0
1
0
11 10 9 8 7 6 5 4 3 2 1 0
1
0
11 10 9 8 7 6 5 4 3 2 1 0
1
0
11 10 9 8 7 6 5 4 3 2 1 0
1
0
6
5
4
3
2
1
0