User guide

22-16
SystemVerilog Design Constructs
log2[15][1][4]=1;
Here is an example in which some dimensions are packed, but
another is not:
logic [11:0][1:0] log3 [6:0];
Here are seven entries of three bytes. In an assignment to this array,
you reference the unpacked dimensions, followed by the packed
ones. To assign to the left-most bit in the left most dimensions, do
the following:
log3[6][11][1]=1;
In these assignments the last packed dimension can be a part select,
or a slice. For example:
log3[6][11][1:0]=2’b11;
log3[6][11:10]=2’b00;
Indexing and Slicing Arrays
SystemVerilog has both part-selects and slices. To illustrate this
concept, consider the last example multidimensional array:
logic [11:0][1:0] log3 [6:0];
A graphic representation of the packed and unpacked dimensions of
this array is in Figure 22-1.