User guide

22-15
SystemVerilog Design Constructs
When assigning to a packed array you can assign any vector
expression, for example:
bit [1:0] b1; // packed array
bit signed [10:0] b2; // packed array
logic [7:0] l2; // packed array
.
.
.
b1={r1,r2};
b2=’1;
l2=b2[7:0];
Multiple Dimensions
You can have multi-dimensional arrays where all the dimensions are
packed or some dimensions are packed and others unpacked. Here
is an example of all dimensions packed:
logic [7:0][3:0][9:0] log1;
Here, is a single entry of forty bytes. All dimensions are packed, so
in an assignment to this array, you reference the dimensions from left
to right. To assign to the left-most bit in the left most dimensions, do
the following:
log1[7][3][9]=1;
Here is an example of none of the dimensions packed:
logic log2 [15:0][1:0][4:0];
Here are ten entries of two bytes. Like when all dimensions are
packed, when all dimensions are unpacked, in an assignment to this
array, you reference the dimensions from left to right.To assign to the
left-most bit in the left most dimensions, do the following: