User guide

22-14
SystemVerilog Design Constructs
initial
s2 = {default:0};
SystemVerilog Arrays
SystemVerilog has packed and unpacked arrays. In a packed array
all the dimensions are specified to the left of the variable name. In an
unpacked array the dimensions are to the right of the variable name.
For example:
bit [1:0] b1; // packed array
bit signed [10:0] b2; // packed array
logic l1 [31:0]; // unpacked array
Packed arrays can only have the following variable data types: bit,
logic, and reg. You can make a packed array of any net data type.
Unpacked arrays can be made of any data type.
When assigning to and from an unpacked array the following rules
must be followed:
• You cannot assign to them an integer, for example:
logic l1 [31:0]; // unpacked array
.
.
.
l1 = ’0;
• You cannot treat them as an integer in an expression, for example:
logic l1 [31:0]; // unpacked array
.
.
.
reg2 = (l1 + 2);
• You can only assign another unpacked array with the same
number of dimensions, all with the same size.