User guide

22-12
SystemVerilog Design Constructs
mbit1=lr[23:8];
mbit2=lr[7:0];
$display("mbit1=%0b mbit2=%0b",mbit1,mbit2);
end
In SystemVerilog you can enter an unsized literal single bit preceded
by an apostrophe ’ as shown in the assignments to members left
and right. All bits the variable are assigned the unsized literals single
bit. In this case left is filled with ones and right is filled with zeroes.
Here the $display system task displays the following:
mbit1=1111111111111111 mbit2=0
VCS has not implemented an unpacked union. In a packed union all
members must be packed structures, packed arrays (see
"SystemVerilog Arrays" on page 22-14), or integer data types, all with
the same size, for example:
typedef struct packed { bit [15:0] b1; bit [7:0] b2;} st24;
typedef union packed{
st24 st24_1;
reg [23:0] r1;
reg [7:0][2:0] r2;
} union1;
In this union all the members, structure st24, reg r1, and reg r2 have
24 bits.
You can access the members of the union as follows:
union1 u1;
bit [7:0] mybit1;
reg [7:0]myreg1;
initial
begin
mybit1=u1.st24_1.b2;