User guide

22-11
SystemVerilog Design Constructs
logic1 = st1.lg1;
longint1 = st3.st2.lg1;
st1.bt1 = bit1;
end
You can make assignments to an entire structure if you also make
the structure a user-defined type. For example:
typedef struct { logic [7:0] lg2; bit [2:0] bit2;} st4;
st4 st4_1;
initial
st4_1={128,3};
The keyword typedef makes the structure a user-defined type. Then
we can declare a variable of that type. Then we can assign values to
the members of the structure. Here lg2 is assigned 128 and bit2 is
assigned 3.
A structure can be packed or unpacked. A packed structure is packed
in memory without gaps so that its members represent bit or part
selects of a single vector. This isn’t true with unpacked structures.
You specify a packed structure with the packed keyword. By default
structures are unpacked. The following is an example of a packed
structure:
struct packed { bit [15:0] left; bit [7:0] right;} lr;
With a packed structure you can access the values of the members
by accessing bit or part selects of the packed structure’s vector. For
example:
initial
begin
lr.left=’1;
lr.right=’0;