User guide

2-15
Modeling Your Design
To avoid these debugging problems, and to increase simulation
performance, do the following when writing new models:
1. If you need values to propagate in and out of a port, declare it as
an inout port. If you don’t need this bidirectional behavior, declare
it as an input or output port.
2. Compile the modules with these ports under the ‘noportcoerce
compiler directive.
Creating Models That Simulate Faster
When modeling your design, for faster simulation use higher levels
of abstraction. Behavioral and RTL models simulate much faster that
gate and switch level models. This rule of thumb is not unique to VCS;
it applies to all Verilog simulators and even all logic simulators in
general.
What is unique to VCS are the acceleration algorithms that make
behavioral and RTL models simulate even faster. In fact VCS is
particularly optimized for RTL models for which simulation
performance is critical.
These acceleration algorithms work better for some designs than for
others. Certain types of designs prevent VCS from applying some of
these algorithms. This section describes the design styles that
simulate faster or slower.
The acceleration algorithms apply to most data types and primitives
and most types of statements but not all of them. This section also
describes the data types, primitives, and types of statements that you
should try to avoid.