User guide

22-9
SystemVerilog Design Constructs
module test;
logic [31:0] log1,log2;
bit [7:0] bit1;
parameter type bus_t = $typeof(log1);
In this type parameter, bus_t gets the data type of log1, which is
logic[31:0].
initial
begin
if ($typeof(log1) == $typeof(log2))
$display("log1 same data type as log2");
if ($typeof(log1) != $typeof(bit1));
$display("log1 not the same data type as bit1");
if ($typeof(log2) == $typeof(logic [31:0]))
$display("log2 is logic [31:0]");
VCS executes all three of these $display system tasks. Notice that
the argument to the second $typeof system function, in the last if
statement, is not a signal name but a data type. This is the way of
determining if a signal’s data type is a specified data type.
end
endmodule
Be advised that you cannot use this system function to supply a data
type at the start of a signal declaration. The following is invalid:
$typeof(log1) log2;
Specifying the wrong kind of argument results in the following error
message:
Error-[SVFNYI] System Verilog feature not yet implemented
$typeof system function is currently supported only for
primary expressions, selects and slices on primary
expressions, structure member references and data types.