User guide

22-5
SystemVerilog Design Constructs
User-Defined Data Types
You can define your own data types from other data types using the
typedef construct like in C. For example:
typedef logic [63:0] mylog;
mylog m1, m2, m3, m4;
Following the typedef keyword are the SystemVerilog data type for
the user-defined type, the optional bit-width, and the name of the
user-defined type.
You can use a user-defined type, that is, declare a signal that has a
user-defined type, before the definition of the user-defined type. For
example:
typedef mine;
mine p;
.
.
.
typedef int mine;
You enable this use of a user-defined type by entering the typedef
keyword and the name of the user-defined type without the
SystemVerilog data type.
Enumerations
You can declare a set of variables that have a set of values. These
are called enumerated data types. For example:
enum shortint{green,yellow,red} northsouth,eastwest;