User guide

22-2
SystemVerilog Design Constructs
• Interfaces
• Enabling SystemVerilog
• Disabling unique And priority Warning Messages
SystemVerilog Data Types
SystemVerilog has several new data types which are described in
the following sections.
Variable Data Types for Storing Integers
VCS has implemented the following SystemVerilog variable data
types for storing integers:
Notice that some of these data types default to signed values. The
Verilog-2001 standard has the unsigned reserved keyword. In
SystemVerilog you can use it in the variable declaration to change
one of these default signed data types to unsigned. For example:
longint unsigned liu;
data type States Default Description
char
two state signed A C-like data type, 8-bit integer
shortint
two state signed 16-bit integer
int
two state signed 32-bit integer
longint
two state signed 64-bit integer
byte
two state signed 8-bit integer or ASCII character
bit
two state unsigned User-defined vector size
logic
four state unsigned User-defined vector size