User guide

2-14
Modeling Your Design
Here both the +define+comppostprocess compile-time option
and the +runpostprocess runtime option are required for VCS to
write the VPD file. This technique allows you to avoid recompiling just
to prevent VCS from writing the file during the next simulation and
also provides you with a way to recompile the testbench, later in the
development cycle, to exclude these system tasks without first editing
the source code for the testbench.
Avoiding the Debugging Problems From Port Coercion
The first Verilog simulator had a port collapsing algorithm that
removed ports so it could simulate faster. In this simulator, you could
still refer to a collapsed port, but inside the simulator, the port did not
exist.
VCS mimics port collapsing so that an old but reusable design, now
simulated with VCS, will have the same simulation results. For this
reason the default behavior of VCS is to “coerce” all ports to inout
ports.
This port coercion can, for example, result in a value propagating up
the design hierarchy out of a port you declared to be an input port
and unexpectedly driving the signal connected to this input port. Port
coercion, therefore, can cause debugging problems.
Port coercion also results in slower simulation, because with port
coercion VCS must be prepared for bidirectional behavior of input
and output ports as well as inout ports.