User guide

21-97
OpenVera Native Testbench
VCS compile:
vcs -sverilog -ntb_opts interop +Other_NTB_options
-ntb_incdir incdir1+incdir2+...
-ntb_define defines_for_OV_source_files
OpenVera_.vrp_files
OpenVera_source_files_.vr
SystemVerilog_source_files_and_libraries
A few more compile options are significant:
1. if RVM class libs are used in the OV code, this is required:
-ntb_opts rvm
2. VMM classes, vmm_ macros can be used in SV; and rvm_ macros
in OV package are automatically translated to vmm_ equivalents if
this is also added
-ntb_opts interop -ntb_opts rvm
Limitations
Classes extended/defined in SystemVerilog cannot be instantiated
by OpenVera. OpenVera verification IP will need to be compiled with
the NTB syntax and semantic restrictions. These restrictions are
detailed in the Vera to Native Testbench coding Guide, included in
the VCS release.
SystemVerilog contains several data types that are not supported in
OpenVera including real, unpacked-structures, and unpacked-
unions. OpenVera cannot access any variables or class data
members of these types. A compiler error will occur if the OpenVera
code attempts to access the undefined SystemVerilog data member.
This does not prevent SystemVerilog passing an object to OpenVera,