User guide

21-95
OpenVera Native Testbench
• In SystemVerilog code, SystemVerilog syntax must be used to
turn off/on constraint blocks or randomization of specific rand
variables (even for OpenVera classes).
• Random stability will be maintained across the language domain.
//OV
class OVclass{
rand integer ri;
constraint cnst{...}
}
//SV
OVclass obj=new();
SVclass Svobj=new();
SVobj.randomize();
obj.randomize() with
{obj.ri==SVobj.var;};
Functional Coverage
There are some differences in functional coverage semantics
between OpenVera and SystemVerilog. These differences are
currently being eliminated by changing OpenVera semantics to
conform to SystemVerilog. In interoperability mode,
coverage_group in OpenVera and covergroup in SystemVerilog
will have the same (SystemVerilog) semantics. Non-embedded
coverage group can be imported from Vera to SystemVerilog using
the package import syntax (similar to classes).
Coverage reports will be unified and keywords such as coverpoint,
bins will be used from SystemVerilog instead of OpenVera keywords.
Here is an example of usage of coverage groups across the language
boundary:
// OpenVera