User guide

2-12
Modeling Your Design
No matter whether you enter the +a, +ab, or +abc plusarg, when you
simulate the executable, VCS always displays the following:
<<< Now a >>>
To avoid this pitfall, enter the longest plusarg first. For example, you
would revise the previous example as follows:
module top;
initial
begin
if ( $test$plusargs("abc") )
$display("\n<<< Now abc >>>\n");
else if ( $test$plusargs("ab") )
$display("\n<<< Now ab >>>\n");
else if ( $test$plusargs("a") )
$display("\n<<< Now a >>>\n");
end
endmodule
Advantages and Disadvantages
The advantage to using this technique is that you do not have to
recompile the testbench in order to stop VCS from writing the VPD
file. This technique is something to consider using, particularly early
in the development cycle of your design, when you are fixing a lot of
bugs and already doing a lot of recompilation.
The disadvantages to this technique are considerable. Compiling
these system tasks, or any system tasks that write to a file, into the
testbench requires VCS to compile the simv executable so that it is
possible for it to write the VPD file when the runtime option is included
on the command line. This means that the simulation runs significantly
slower than if you don’t compile these system tasks into the testbench.
This impact on performance remains even when you don’t include
the runtime option on the simv command line.