User guide

21-93
OpenVera Native Testbench
// SystemVerilog
interface IFC(input clk);
wire a;
wire b;
clocking cb @(posedge clk);
output a;
input b;
endclocking
modport mp (clocking cb, import cb.*);
endinterface: IFC
import OpenVera::Foo;
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IFC ifc(clk); // use this to connect to DUT and TB
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virtual IFC.mp vmp = ifc.mp;
Foo f = new(vmp); // clocking event of ifc.cb mapped to
// $clk in port P
// ifc.cb.a mapped to $a in port P
// ifc.cb.b mapped to $b in port P
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f.foo();
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Note:
It is not necessary to use a virtual modport above. One can directly
pass a modport from an instance of an interface as follows:
Foo f = new(ifc.mp);
A modport can aggregate signals from multiple clocking blocks.
Semantic Issues with Samples, Drives, and Expects
When OpenVera code wants to sample a DUT signal through a virtual
port (or interface), if the current time is not at the relevant clock edge,