User guide

21-91
OpenVera Native Testbench
bit clk;
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IFC i(clk);
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virtual IFC.mp vmp;
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vmp = i.mp;
@(vmp.a); // cb can be omitted; 'cb.a' is
// imported into the modport
// Example-2
interface IFC(input clk);
wire a, b;
bit clk;
clocking cb @(posedge clk);
input a;
input b;
endclocking
modport mp (import cb.*); // All members of cb
// are imported.
// Equivalent to the
// modport in
// Example-1.
endinterface
bit clk;
.
.
.
IFC i(clk);
.
.
.
virtual IFC.mp vmp;
.
.
.
vmp = i.mp;
@(vmp.a); // cb can be omitted;
//'cb.a' is imported into the modport
A SystemVerilog modport can be implicitly converted to an OpenVera
virtual port provided the following conditions are satisfied: