User guide

21-90
OpenVera Native Testbench
Importing Clocking Block Members into a Modport
VCS allows a reference to a clocking block member to be made by
omitting the clocking block name.
For example, in SystemVerilog a clocking block is used in a modport
as follows:
interface IFC(input clk);
wire a, b;
clocking cb @(posedge clk);
input a;
input b;
endclocking
modport mp (clocking cb);
endinterface
bit clk;
.
.
.
IFC i(clk);
.
.
.
virtual IFC.mp vmp;
.
.
.
vmp = i.mp;
@(vmp.cb.a); // here we need to specify cb explicitly
VCS supports the following extensions that allow the clocking block
name to be omitted from vmp.cb.a.
// Example-1
interface IFC(input clk);
wire a, b;
clocking cb @(posedge clk);
input a;
input b;
endclocking
modport mp (import cb.a, import cb.b);
endinterface