User guide

21-89
OpenVera Native Testbench
OpenVera: they will be implicitly converted to bit vectors of the same
width.
packed struct {...} s in SystemVerilog is mapped to
reg [m:0] r in OpenVera where m == $bits(s).
Analogous mapping applies to unions.
Connecting to the Design
Mapping Modports to Virtual Ports
This section relies on the following extensions to SystemVerilog
supported in VCS.
Virtual Modports
VCS supports a reference to a modport in an interface to be declared
using the following syntax.
virtual interface_name.modport_name virtual_modport_name;
For example:
interface IFC;
wire a, b;
modport mp (input a, output b);
endinterface
IFC i();
virtual IFC.mp vmp;
.
.
.
vmp = i.mp;