User guide

21-87
OpenVera Native Testbench
Arrays
Arrays can be passed as arguments to tasks and functions from
SystemVerilog to OpenVera and vice-versa. The formal and actual
array arguments must have equivalent element types, the same
number of dimensions with corresponding dimensions of the same
length. These rules follow the SystemVerilog LRM.
• A SystemVerilog fixed array dimension of the form [m:n] is
directly mapped to [abs(m-n)+1] in OpenVera.
• An OpenVera fixed array dimension of the form [m] is directly
mapped to [m] in SystemVerilog.
Rules for equivalency of other (non-fixed) types of arrays are as
follows:
• A dynamic array (or Smart queue) in OpenVera is directly mapped
to a SystemVerilog dynamic array if their element types are
equivalent (can be directly mapped).
• An OpenVera associative array with unspecified key type (for
example integer a[]) is equivalent to a SystemVerilog
associative array with key type reg [63:0] provided the element
types are equivalent.
• An OpenVera associative array with string key type is
equivalent to a SystemVerilog associative array with string key
type provided the element types are equivalent.
Other types of SystemVerilog associative arrays have no equivalent
in OpenVera and hence they cannot be passed across the language
boundary.