User guide

21-86
OpenVera Native Testbench
Integers and Bit-Vectors
The mapping between SystemVerilog and OpenVera integral types
are shown in the table below.
Note:
If a value or sign conversion is needed between the actual and
formal arguments of a task or function, then the argument cannot
be passed by reference.
Of additional interest is the reverse map for the OV bit type:
SystemVerilog OpenVera
2/4 or 4/2 value
conversion?
Change in
signedness?
integer integer N
(equivalent types)
N (Both signed)
byte reg [7:0] Y Y
shortint reg [15:0] Y Y
int integer Y N (Both signed)
longint reg [63:0] Y Y
logic [m:n] reg [abs(m-n)+1:0] N
(equivalent types)
N (Both unsigned)
bit [m:n] reg [abs(m-n)+1:0] Y N (Both unsigned)
time reg [63:0] Y N (Both unsigned)
OV SV 2/4 or
change in
4/2 signedness?
conv?
bit[m:n] logic[m:n]N N