User guide

21-85
OpenVera Native Testbench
Enumerated types with 2-value base types will be implicitly converted
to the appropriate 4-state type (of the same bit length). See the
discussion in 2.5 on the conversion of bit vector types.
OpenVera enum types can be imported to SystemVerilog using the
following syntax:
import OpenVera::openvera_enum_name;
It will be used as follows:
// OpenVera
enum OpCode { Add, Sub, Mul };
// System Verilog
import OpenVera::OpCode;
OpCode x = OpenVera::Add;
// or the enum label can be imported and then used
// without OpenVera::
import OpenVera::Add;
OpCode y = Add;
Note:
- SystemVerilog enum methods such as next, prev and name
can be used on imported OpenVera enums.
Enums contained within OV classes are illustrated in this example:
class OVclass{
enum Opcode {Add, Sub, Mul};
}
import OpenVera::OVclass;
OVclass::Opcode SVvar;
SVvar=OVclass::Add;