User guide

21-80
OpenVera Native Testbench
import OpenVera::Base;
Data Type Mapping
In this section, we describe how various data types in SystemVerilog
are mapped to OpenVera and vice-versa.
• Direct mapping: Many data types have a direct mapping in the
other language and no conversion of data representation is
required. In such cases, we say that the OpenVera type is
equivalent to the SystemVerilog type.
• Implicit conversion: In other cases, VCS performs implicit type
conversion. The rules of inter language implicit type conversion
follows the implicit type conversion rules specified in
SystemVerilog LRM. To apply SystemVerilog rules to OpenVera,
the OpenVera type must be first mapped to its equivalent
SystemVerilog type. For example, there is no direct mapping
between OpenVera reg and SystemVerilog bit. But reg in
OpenVera can be directly mapped to logic in SystemVerilog.
Then the same implicit conversion rules between SystemVerilog
logic and SystemVerilog bit can be applied to OpenVera reg
and SystemVerilog bit.
• Explicit translation: In the case of mailboxes and semaphores, the
translation must be explicitly performed by the user. This is
because in OpenVera, mailboxes and semaphores are
represented by integer ids and VCS cannot reliably determine
if an integer value represents a mailbox id.