User guide

21-77
OpenVera Native Testbench
Importing OpenVera types into SystemVerilog
OpenVera has two user defined types: enums and classes. These
types can be imported into SystemVerilog by using SystemVerilog
package import syntax:
import OpenVera::openvera_class_name;
import OpenVera::openvera_enum_name;
Allows one to use openvera_class_name in SystemVerilog code
in the same way as an SystemVerilog class. This includes the ability
to:
• Create objects of type openvera_class_name
• Access or use properties and types defined in
openvera_class_name or its base classes,
• Invoke methods (virtual and non-virtual) defined in
openvera_class_name or its base classes
• Extend openvera_class_name to SV classes
This does not however import the names of base classes of
openvera_class_name into SystemVerilog (that requires an
explicit import). For example:
// OpenVera
class Base {
.
.
.
task foo(arguments) {
.
.
.
}
virtual task (arguments) {
.
.
.