User guide

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OpenVera Native Testbench
• The automatic mapping of data types between the two languages
as well as the limitations of this mapping (some data types cannot
be directly mapped).
• Working with synchronization objects such as events, mailboxes
and semaphores across the language boundary.
• Mapping of SystemVerilog modports to OpenVera where they can
be used as OpenVera virtual ports.
• Effect of directly or indirectly calling blocking OpenVera functions
from SystemVerilog.
• Handling of differences in the semantics of sample, drive, expect,
etc. between OpenVera and SystemVerilog.
• The OpenVera-SystemVerilog interoperability use model.
Scope of Interoperability
The scope of OpenVera-SystemVerilog interoperability in VCS Native
Testbench is as follows:
• Classes defined in OpenVera, that you use directly or extend in
a SystemVerilog testbench
• A testbench in SystemVerilog. The testbench uses SystemVerilog
constructs like interfaces with modports, virtual interfaces with
modports, and clocking blocks to communicate with the design.
• OpenVera code does not contain program blocks, interfaces, bind
statements, classes, enums, ports, tasks and functions.
•Your OpenVera code uses virtual ports for sampling, driving or
waiting on design signals that are connected to the SystemVerilog
testbench.