User guide

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OpenVera Native Testbench
Simulation:
% simv runtime_sva_options
Running OpenVera Testbench with SVA and OVA
Together
Compilation:
vcs ov_options_&_ov_files ova_&_ova_options \
sva_options_&_sva_files +sysvcs
Simulation:
simv simv_options
OpenVera-SystemVerilog Testbench Interoperability
The primary purpose of OpenVera-SystemVerilog interoperability in
VCS Native Testbench is to enable you to reuse OpenVera classes
in new SystemVerilog code without rewriting OpenVera code into
SystemVerilog.
This section describes:
• The Scope of Interoperability
• Using the SystemVerilog package import syntax to import
OpenVera data types and constructs into SystemVerilog.
• Calling of OpenVera tasks, functions and methods from
SystemVerilog. Tasks and functions can be imported to
SystemVerilog using the same method for importing classes.