User guide

2-10
Modeling Your Design
Later in the development cycle of the design, you can compile the
design without the +define+postprocess compile-time option
and VCS will not compile these system tasks into the testbench. Doing
so enables VCS to simulate your design much faster.
Advantages and Disadvantages
The advantage of this technique is that simulation can run faster than
if you enable debugging features at runtime. When you use
conditional compilation VCS has all the information it needs at
compile-time.
The disadvantage of this technique is that you have to recompile the
testbench to include these system tasks in the testbench, thus
increasing the overall compilation time in the development cycle of
your design.
Synopsys recommends that you consider this technique as a way to
prevent these system tasks from inadvertently remaining compiled
into the testbench, later in the development cycle, when you want
faster performance.
Enabling Debugging Features At Runtime
Use the $test$plusargs system function in place of the ‘ifdef
compiler directives. The $test$plusargs system function checks
for a plusarg runtime option on the simv command line.
Note:
A plusarg option is an option that has a plus (+) symbol as a prefix.