User guide

2-9
Modeling Your Design
Conditional Compilation
Use ‘ifdef, ‘else, and ‘endif compiler directives in your
testbench to specify which system tasks you want to compile for
debugging features. Then, when you compile the design with the
+define compile-time option on the command line (or when the
‘define compiler directive appears in the source code), VCS will
compile these tasks for debugging features. For example:
initial
begin
`ifdef postprocess
$vcdpluson(0,design_1);
$vcdplustraceon(design_1);
$vcdplusdeltacycleon;
$vcdplusglitchon;
`endif
end
In this case, the vcs command is as follows:
% vcs testbench.v design.v +define+postprocess
The system tasks in this initial block record several types of
information in a VPD file. You can use the VPD file with DVE to
post-process the design. In this particular case, the information is for
all the signals in the design, so the performance cost is extensive.
You would only want to do this early in the development cycle of the
design when finding bugs is more important than simulation speed.
The command line includes the +define+postprocess
compile-time option, which tells VCS to compile the design with these
system tasks compiled into the testbench.