User guide

2-8
Modeling Your Design
Optimizing Testbenches for Debugging
Testbenches typically execute debugging features, for example,
displaying text in certain situations as specified with the $monitor
or $display system tasks. Another debugging feature, which is
typically enabled in testbenches, is writing simulation history files
during simulation so that you can view the results after simulation.
Among other things, these simulation history files record the
simulation times at which the signals in your design change value.
These simulation history files can be either ASCII
Value-Change-Dump (VCD) files that you can input into a number of
third party viewers, or binary VPD files that you can input into DVE.
The $dumpvars system task specifies writing a VCD file and the
$vcdpluson system task specifies writing a VPD file. You can also
input a VCD file to DVE, which translates the VCD file to a VPD file
and then displays the results from the new VPD file. For details on
using DVE, see the Discovery Visual Environment User Guide.
Debugging features significantly slow down the simulation
performance of any logic simulator including VCS. This is particularly
true for operations that make VCS display text on the screen and
even more so for operations that make VCS write information to a
file. For this reason, you’ll want to be selective about where in your
design and where in the development cycle of your design you enable
debugging features. The following sections describe a number of
techniques that you can use to choose when debugging features are
enabled.