User guide

2-7
Modeling Your Design
Time Zero Race Conditions
The following race condition is subtle but very common:
always @(posedge clock)
$display("May or may not display");
initial begin
clock = 1;
forever #50 clock = ~clock;
end
This is a race condition because the transition of clock to 1 (posedge)
may happen before or after the event trigger (always @(posedge
clock)) is established. Often the race is not evident in the simulation
result because reset occurs at time zero.
The solution to this race condition is to guarantee that no transitions
take place at time zero of any signals inside event triggers. Rewrite
the clock driver in the above example as follows:
initial begin
clock = 1’bx;
#50 clock = 1’b0;
forever #50 clock = ~clock;
end