User guide

21-28

OpenVera Native Testbench

vcs -ntb_vl dut.v name.test_top.v tb.vshell

Here:

-ntb_vl

Specifies the compilation of all Verilog files, including the design,

the testbench shell file and the top-level Verilog module.

Example

% vcs -ntb_vl sram.v sram.test_top.v sram.vshell

Note:

Remember, if, for example, you used -debug_all when

compiling the .vr file, you must include -debug_all on the vcs

command line as well. For example:

% vcs -debug_all -ntb_vl dut.v name.test_top.v tb.vshell

Loading the Compiled Testbench On simv

Finally, load the compiled testbench shared object file, libtb.so, on

simv using the following syntax:

% simv +ntb_load=path_name_to_libtb.so

% simv +ntb_load=./libtb.so

Here:

+ntb_load

Specifies the testbench shared object file libtb.so to be loaded.