User guide

21-27
OpenVera Native Testbench
-ntb_spath
Specifies the directory where the testbench shell and shared
object files will be generated. The default is the compilation
directory.
-ntb_noshell
Specifies not generating the shell file. Use this only when you are
recompiling a testbench.
-ntb_shell_only
Generates only the .vshell file. Use this only when you are
compiling a testbench separately from the design file.
Note:
When compiling the testbench files separately from the design,
the following rules apply:
- Specify the ntb options should be specified only during
testbench compilation. The exception is the -ntb_vl option that
specifies that the DUT is compiled separately and which you
should therefore specify while compiling the DUT.
- Specify ‘C’ files or other library files should be specified only
while compiling the DUT. These options are ignored for
testbench compilation.
- Specify all other tool options for both testbench and DUT
compilation. For example, -debug_all, -debug, etc.
Compiling the Design, the Testbench Shell And the
Top-level Verilog Module
Next you generate a simv for your design. The syntax for compiling
the Verilog design file, dut.v, with the testbench shell (tb.vshell) and
the top-level Verilog module (test_top.v) is the following: