User guide

21-26
OpenVera Native Testbench
The following steps demonstrate a typical flow involving separate
compilation of the testbench:
1. Compile the testbench in VCS to generate the shared object
(libtb.so) file containing the compiled testbench and the Verilog
testbench shell file.
2. Compile the Verilog design along with the top-level Verilog
module and the testbench shell (.vshell) file to generate the
executable simv.
3. Load the testbench on simv at runtime.
Separate Compilation of Testbench Files for VCS
To compile the testbench file (tb.vr) and create the testbench shell
(.vshell) and shared object (libtb.so) files, use the following syntax:
vcs -ntb_cmp [-ntb_options] [-ntb_noshell | \
-ntb_shell_only] tb.vr
Here:
-ntb_cmp
Compiles and generates the testbench shell (file.vshell) and
shared object files
Compile-time Options
-ntb_sfname filename
Specifies the file name of the testbench shell.
-ntb_sname module_name
Specifies the name of the testbench shell module.