User guide

21-25
OpenVera Native Testbench
Compiling the Testbench Separate From the OpenVera
Design
This section describes how to compile your testbench separately
from your design and then load it on simv (compiled design
executable) at runtime. Separate compilation of testbench files
allows you to:
• Keep one or many testbenches compiled and ready and then
choose which testbench to load when running a simulation.
• Save time by recompiling only the testbench after making
changes to it and then running simv with the recompiled
testbench.
• Save time in cases where changes to the design do not require
changes to the testbench by recompiling only the design after
making changes to it and then running simv with the previously
compiled testbench.
Separate compilation of the testbench generates two files:
• The compiled testbench in a shared object file, libtb.so. This
shared object file is the one to be loaded on simv at runtime.
• A Verilog shell file (.vshell) that contains the testbench shell
module. Since the testbench instance in the top-level Verilog
module now refers to this shell module, the shell file has to be
compiled along with the design and the top-level Verilog module.
The loaded shared object testbench file is automatically invoked
by the shell module during simulation.