User guide

21-24
OpenVera Native Testbench
Compiling and Running the OpenVera Testbench
This section describes how to compile your testbench with the
design and how to compile the testbench independently from the
design. It also describes compile-time and runtime options.
In order to ease transitioning of legacy code from Vera’s
make-based single-file compilation scheme to VCS, where all source
files have to be specified on the command line, VCS provides a way
of instructing the compiler to reorder Vera files in such a way that
class declarations are in topological order. The following sections
describe how to do this.
Compiling the Testbench with the OpenVera Design
The VCS command line for compiling both your testbench and
design is the following:
% vcs -ntb design_module_name.v module_name.test_top.v
testbench_file.vr [vcs_compile-time_options]
[ntb_compile-time_options]
The compilation results in a single executable simv that contains
both testbench and design information.
For a list of NTB compile-time options, see Options for OpenVera
Native TestBench in Appendix B.
The command line for running the simulation is as follows:
% simv +vcs_runtime_options