User guide

2-5
Modeling Your Design
Note that the following change does not resolve the race condition:
always @(posedge clk)
#1 q = d; // race!
The #1 delay simply shifts the original race by one time unit, so that
the intermediate node is set and sampled one time unit after the
posedge of clock, rather than on the posedge of clock. Avoid this
coding style.
Continuous Assignment Evaluation
Continuous assignments with no delay are sometimes propagated
earlier in VCS than in Verilog-XL. This is fully correct behavior, but
exposes race conditions such as the one in the following code
fragment:
assign x = y;
initial begin
y = 1;
#1
y = 0;
$display(x);
end
In VCS, this displays 0, while in Verilog-XL, it displays 1, because the
assignment of the value to x races with the usage of that value by the
$display.
Another example of this type of race condition is the following:
assign state0 = (state == 3'h0);
always @(posedge clk)
begin
state = 0;