User guide

21-23
OpenVera Native Testbench
output [7:0] q2 ;
input rst_ ;
input clk ;
dff u1 (.q(q1), .d(d1), .rst_(rst_), .clk(clk)) ;
dff u2 (.q(q2), .d(d2), .rst_(rst_), .clk(clk)) ;
endmodule
module dff (q, d, rst_, clk) ;
input [7:0] d ;
output [7:0] q ;
input rst_ ;
input clk ;
reg [7:0] q ;
always @(posedge clk)
q <= (!rst_)? 8'h00 : d ;
endmodule
// vlog.f
duv.v
top.v
// config.vrl
program
./test1.vr
program
./test2.vr
// 1_comp_run_ntb
#!/bin/csh -fx
vcs -ntb -f vlog.f -ntb_opts config=config.vrl
simv