User guide

21-22
OpenVera Native Testbench
@1 duv1.d = 2 ;
@1 duv1.d = 3 ;
@20 duv1.q == 8'h3 ;
printf("end of sim duv_test1\n") ;
}
// duv.if2.vri
#ifndef INC_DUV2_IF_VRH
#define INC_DUV2_IF_VRH
interface duv2 {
input [7:0] q PSAMPLE #-1;
inout [7:0] d PDRIVE #1 PSAMPLE #-1 ;
output rst_ PDRIVE #1 ;
input clk CLOCK ;
} // end of interface duv
#endif
// test2.vr
#include <vera_defines.vrh>
#include "duv.if2.vri"
program duv_test2 {
printf("start of sim duv_test2\n") ;
@1 duv2.rst_ = 0 ;
@1 duv2.rst_ = 1 ;
@1 duv2.rst_ = void ;
@1 duv2.d = 1 ;
@1 duv2.d = 2 ;
@1 duv2.d = 3 ;
@2 duv2.q == 8'h3 ;
@1 duv2.d = 3 ;
printf("end of sim duv_test2\n") ;
}
// dut.v
module duv ( q1, d1, q2, d2, rst_, clk) ;
input [7:0] d1 ;
output [7:0] q1 ;
input [7:0] d2 ;