User guide

21-21
OpenVera Native Testbench
.d2 (d2),
.rst_ (rst_),
.clk (clk),
.q1 (q1),
.q2 (q2)
);
initial begin
SystemClock = 0;
forever begin
#(simulation_cycle/2)
SystemClock = ~SystemClock;
end
end
endmodule
// duv.if1.vri
#ifndef INC_DUV1_IF_VRH
#define INC_DUV1_IF_VRH
interface duv1 {
input [7:0] q NSAMPLE ;
inout [7:0] d PDRIVE #1 PSAMPLE #-1 ;
output rst_ PDRIVE ;
input clk CLOCK ;
} // end of interface duv
// hdl_node CLOCK "duv_test_top.clk";
#endif
// test1.vr
#include <vera_defines.vrh>
#include "duv.if1.vri"
program duv_test1 {
printf("start of sim duv_test1\n") ;
@1 duv1.rst_ = 0 ;
@1 duv1.rst_ = 1 ;
@1 duv1.rst_ = void ;
@1 duv1.d = 1 ;