User guide

2-4
Modeling Your Design
Flip-Flop Race Condition
It is very common to have race conditions near latches or flip-flops.
Here is one variant in which an intermediate node a between two
flip-flops is set and sampled at the same time:
module test(out,in,clk);
input in,clk;
output out;
wire a;
dff dff0(a,in,clk);
dff dff1(out,a,clk);
endmodule
module dff(q,d,clk);
output q;
input d,clk;
reg q;
always @(posedge clk)
q = d; // race!
endmodule
The solution for this case is straightforward. Use the nonblocking
assignment in the flip-flop to guarantee the order of assignments to
the output of the instances of the flip-flop and sampling of that output.
The change looks like this:
always @(posedge clk)
q <= d; // ok
Or add a nonzero delay on the output of the flip-flop:
always @(posedge clk)
q = #1 d; // ok
Or use a nonzero delay in addition to the nonblocking form:
always @(posedge clk)
q <= #1 d; // ok