User guide

21-10
OpenVera Native Testbench
% ntb_template -t design_module_name [ -c clock] filename.v \
[-vcs vcs_compile-time_options]
Here:
design_module_name
The name of the module of your design.
The following template-generator command line illustrates all
possible options:
% ntb_template -t arb -c clk arb.v -vcs vcs_option \
[-vcs vcs_compile-time_options]
-t
Specifies the top-level design module name.
arb
Name of the top-level design module.
arb.v
Name of the design file.
-c
Specifies the clock input of the design.
-vcs
Specifies any VCS command that needs to be used in template
generation. For example, if the top-level design module has ports
listed in the Verilog-2001 format (v2k), then you need to specify
the following: -vcs +v2k.