User guide

21-1
OpenVera Native Testbench
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OpenVera Native Testbench 1
OpenVera Native Testbench is a high-performance, single-kernel
technology in VCS that enables:
• Native compilation of testbenches written in OpenVera and in
SystemVerilog.
• Simulation of these testbenches along with the designs.
This technology provides a unified design and verification
environment in VCS for significantly improving overall design and
verification productivity. Native Testbench is uniquely geared
towards efficiently catching hard-to-find bugs early in the design
cycle, enabling not only completing functional validation of designs
with the desired degree of confidence, but also achieving this goal in
the shortest time possible.