User guide

20-79
Using OpenVera Assertions
Scope resolution follows the Verilog Standard (IEEE Std 1364-2001)
Section 12.5. That is, if a scope argument is specified, then the path
name is first considered as relative to the module where the task was
called. If it does not match any valid relative path, it is matched against
paths one level up. If no match then one more level up, etc. For
example, if scope a.b.c is an argument of a task called from module
m, the scope name is first interpreted as a path starting at an instance
a in m. If such a path does not exist, it is applied to a parent module
of a. If the path does not exist in the root module of m, the path is an
error.
If there are no arguments, that is, $ova_start, the task applies to
the entire design. It is equivalent to $ova_start(0).
To stop monitoring, use the
$ova_stop system task:
$ova_stop[(levels [, module, entity, or scope arguments])];
Whenever this statement is executed, the assertion monitoring stops.
All attempts that are in progress are reset. The command is ignored
if the monitoring has already been stopped in the specified scope or
module.
The integer argument levels indicates how many levels in the
hierarchy at and below the specified modules, entities, and scopes
the OVA monitoring is to stop. Zero indicates all levels below the
specified ones.