User guide

20-68
Using OpenVera Assertions
The first step generates a skeleton Verilog file containing the
hierarchy of the design and the nets converted to registers (for
playback). It also preserves the Verilog parameters. This skeleton
Verilog file must be compiled in the second step before the playback
can occur. It is this compilation step that we will exploit to allow Verilog
parameters to be used in the post-processing flow.
The change to the flow involves the same dummy Verilog file that
was discussed in the sections above. This file, which is disguised as
a Verilog file but, in reality, contains nothing but inlined bind
statements, is passed to the compiler during the -ova_RPP (second)
step. In addition, the -ova_inline and -ova_exp_param options
are added to the -ova_RPP compile step. This will cause the inline
pre-processor to pick up the binds along with the remainder of the
OVA code (which should still be in separate ".ova" files) and expand
the parameters according to the values found in the skeleton design
file.
OVA System Tasks and Functions
OVA system tasks and functions enable you to set conditions and
control the monitoring of assertions, and specify the response to failed
assertions.