User guide

2-1
Modeling Your Design
2
Modeling Your Design 1
Verilog coding style is the most important factor that affects the
simulation performance of a design. How you write your design can
make the difference between a fast error-free simulation, and one
that suffers from race conditions and poor performance. This chapter
describes some Verilog modeling techniques that will help you code
designs that simulate most efficiently with VCS.
This chapter covers the following topics:
• Avoiding Race Conditions
• Optimizing Testbenches for Debugging
• Avoiding the Debugging Problems From Port Coercion
• Creating Models That Simulate Faster
• Case Statement Behavior